About

Currently, I am a Member of Technical Staff in OpenAI’s Research organization, pushing the intelligence frontier for chip design.

I hold a PhD in electrical engineering from UCLA and have 10 years of industry experience working on AI accelerator chips at OpenAI (Jalapeno), Google (TPUs), and SambaNova (RDUs). I’ve held senior roles in hardware and software teams, both as an individual contributor and as a technical lead/manager. I’ve authored and reviewed thousands of PRs and millions of lines of code. My work has landed in nine silicon-proven chips, all of which have successfully deployed or will soon deploy in production at very large scale. And I’ve advised an early-stage AI-for-chip-design startup that successfully exited to a major EDA company. My publication record includes 20 papers and seven patents.

Current interests:

My current work at OpenAI focuses on AI-for-chip-design research; I helped kick off our work in this area. Previously, I was an early member of the team that built Jalapeño, OpenAI’s first custom AI accelerator, designed for LLM inference and developed with Broadcom. I wrote the foundational open source, formally verified RTL libraries before pivoting to help build the software stack from scratch. My software contributions spanned the performance and functional simulators, bit-exact numerics golden reference, runtime, backend compiler, ISA, shared libraries, and silicon bring-up and manufacturing test automation. The team had real workloads running end-to-end in simulation and emulation before our first silicon.

We used our own AI models to accelerate Jalapeño’s design, bring-up, and software optimization. It achieved state-of-the-art inference performance in OpenAI’s reported InferenceX benchmarks, with leading throughput per watt and low latency. Read our first performance results, along with coverage of the project in IEEE Spectrum and SemiAnalysis.

Before joining OpenAI, I was a Senior Manager and Senior Principal Engineer at SambaNova Systems, where I founded and directed the compiler operators team to support the custom Reconfigurable Dataflow Unit (RDU) AI accelerator chip. Our responsibilities included development of internal MLIR dialects, formalization of operators and mixed precision semantics, and implementation of high performance dataflow kernels. As the compiler technical lead for a future RDU chip, I drove several hardware/software codesign efforts and bootstrapped a new architecture specification workflow. I invested significant effort into building the engineering culture, growing the team, and speeding up software builds.

Meanwhile, I was an early Technical Advisor to the founders of ChipStack, a startup that was revolutionizing the way chips are designed and verified. ChipStack was acquired by Cadence in 2025; their technology is central to Cadence’s current AI strategy and product development.

Prior to my work at SambaNova and ChipStack, I was a chip architect, microarchitect, RTL designer, and cross-functional technical lead in Google’s Tensor Processing Unit (TPU) team. All of my projects at Google successfully landed: TPUv4i, TPUv4, TPUv5e, TPUv5p, and Trillium (TPUv6e) have all been key technologies underlying Google’s AI leadership. My contributions to the TPU spanned most of the subsystems, although the bulk of my impact was on the memory system, host interface, and inter-chip interconnect; I won a Feat of Engineering for my work on the TPUv4 on-chip interconnect. Alongside my co-lead, I landed an internal Chip Development Kit (CDK) from scratch. It is a set of comprehensively specified, parameterizable, and formally verified RTL libraries that implement common dataflow primitives with high performance and minimal area. CDK significantly improved the hardware development velocity and lowered bug rates for several different Google chips (not just TPUs) using a correct-by-construction approach. The vast majority of the gates in recent TPU chips are attributed to CDK modules. It was nominated for a Feat of Engineering.

In 2017, I received my Ph.D. in Electrical Engineering from UCLA for my dissertation titled "Opportunistic Memory Systems in Presence of Hardware Variability." My research explored techniques for exploiting inherent imperfections in hardware to improve energy efficiency, reduce cost, and gracefully recover from errors. In 2016, I won the Qualcomm Innovation Fellowship and the UCLA Dissertation Year Fellowship for my co-invention of "Software-Defined Error-Correcting Codes."

I’m a long-time road racing and sports car enthusiast. Whenever not with my family, you are likely to find me road racing in my Spec E46, simracing online, or enjoying Bay Area backroads.