2024-Present
Member of Technical Staff
OpenAI · San Francisco, CA
Working on hardware and AI research in pursuit of the mission to develop artificial general intelligence (AGI) that benefits all of humanity.
Computer architect
Curriculum Vitae
Member of Technical Staff at OpenAI
My current interests are in AI-for-chip-design research, hardware/software codesign of AI chips, and open source hardware and EDA tools.
Experience
2023-2024
Technical Advisor
ChipStack · Mountain View, CA
Moonlighted as technical advisor to ChipStack, a startup that was developing revolutionary AI-based tools for chip design and verification. They were acquired by Cadence in 2025.
2022-2024
Senior Manager/Tech Lead
SambaNova Systems · Palo Alto, CA
Founded and managed the Operators Team that consisted of ten compiler engineers. The team was responsible for formalizing internal MLIR dialects and developing high-performance custom dataflow kernels. Technical lead for the next-generation Reconfigurable Dataflow Unit (RDU); drove hardware/software codesign activities. Architected novel compiler support for mixed precision; led the team to land on a short timeline and enabled improved accuracy for customers. Architected new hardware features to accelerate computer vision models. Bootstrapped a new docs-as-code methodology and created a new dataflow assembly language to enable next-chip architecture spec development. Proposed and implemented a migration of the compiler build from CMake to Bazel to enable >10X speedups for developer workflows. Initiated a collaboration with OpenXLA. Up-leveled the compiler organization by organizing regular knowledge shares and supporting individuals' careers at junior and senior levels. Multiple patents pending.
2017-2022
Senior Hardware Engineer
Google · Sunnyvale, CA
Memory system/NoC, host interface, and inter-chip interconnect architecture, microarchitecture, logic design, and cross-functional technical leadership for multiple generations of Google's Tensor Processing Unit (TPU) datacenter AI accelerator chips (TPUv4i, TPUv4, TPUv5e, TPUv5p, and Trillium). Co-founded the Chip Development Kit (CDK) project which enabled large improvements in development velocity, microarchitecture quality, and verification quality using composable and formally verified libraries along with code generation tools. Pioneered a "correct-by-construction" methodology that has been silicon proven. Led a team of ~15 engineers.
2015
Ph.D. Intern
Microsoft Research · Redmond, WA
Worked in the Sensing and Energy Research Group (SERG) in collaboration with Microsoft Cloud Server Infrastructure. Performance evaluation of memory system fault tolerance schemes for the cloud. Measured and modeled the impact of corrected memory errors on application performance.
2014
Ph.D. Intern
Microsoft Research · Redmond, WA
Worked in the Sensing and Energy Research Group (SERG) in collaboration with Microsoft Cloud Server Infrastructure. Developed X-Mem, an Extensible Memory characterization tool, for exploring the impact of system configurations on cloud server performance.
2012
IP Engineering Intern
Altera (now known as Intel FPGA) · San Jose, CA
RTL design and functional verification of soft IP core to identify malformed PCI Express transaction-layer packets.
2010
Instr. Engr. Co-op
NASA Dryden Flight Research Center (now known as NASA Armstrong FRC) · Edwards AFB, CA
Conducted lab and field tests of GPS and wireless sensor system upgrades for research aircraft.
2009
Flight Syst. Engr. Co-op
NASA Dryden Flight Research Center (now known as NASA Armstrong FRC) · Edwards AFB, CA
Designed, integrated, and documented custom hardware panels for PCBs and wiring harnesses using 3D CAD.
2006-2008
I.T. Intern
Lam Research · Fremont, CA
General I.T. duties, including computer repair and retirement as well as hardware and software troubleshooting.
Education
Ph.D. in Electrical Engineering
University of California, Los Angeles
Dissertation: Opportunistic Memory Systems in Presence of Hardware Variability
Committee: Puneet Gupta, Lara Dolecek, Mani Srivastava, Glenn Reinman
PDFSlides
BiBTeX
@phdthesis{Gottscho2017,
author = {Gottscho, Mark William},
doi = {10.13140/RG.2.2.13446.98885},
keywords = {CAD,DRAM,EDA,IoT,Linux,SRAM,approximate computing,benchmarks,caches,cloud,computer architecture,electronic design automation,embedded systems,error-correcting codes,hardware/software interface,memory systems,operating systems,reliability,resiliency,scratchpads,supercomputers,tools,variation-aware},
school = {University of California, Los Angeles},
title = {{Opportunistic Memory Systems in Presence of Hardware Variability}},
type = {Ph.D. Dissertation},
url = {http://escholarship.org/uc/item/85c1r1q9},
year = {2017}
}M.S. in Electrical Engineering
University of California, Los Angeles
Project: ViPZonE: Exploiting DRAM Power Variability for Energy Savings in Linux x86-64
Advisor: Puneet Gupta
B.S. in Electrical Engineering
University of California, Los Angeles