Curriculum Vitae

Member of Technical Staff

OpenAI · San Francisco, CA

Currently focused on AI-for-chip-design research in OpenAI's Research organization, in pursuit of the mission to develop artificial general intelligence (AGI) that benefits all of humanity. Previously an early member of the team that built Jalapeño, OpenAI's first custom AI accelerator for LLM inference.

• Built the foundational open source, formally verified RTL libraries used to design Jalapeño and future OpenAI chips.
• Helped build the software stack from scratch, contributing to the performance and functional simulators, low-level compiler, runtime, bit-exact numerics model, ISA, shared libraries, and silicon bring-up and manufacturing test tools.
• Contributed to a software stack that ran real workloads end-to-end in simulation and emulation before first silicon.
• Helped kick off OpenAI's work on AI-for-chip-design.

Technical Advisor

ChipStack · Mountain View, CA

Moonlighted as technical advisor to ChipStack, a startup that was developing revolutionary AI-based tools for chip design and verification. They were acquired by Cadence in 2025.

Senior Manager/Tech Lead

SambaNova Systems · Palo Alto, CA

Founded and managed the Operators Team that consisted of ten compiler engineers. The team was responsible for formalizing internal MLIR dialects and developing high-performance custom dataflow kernels. Technical lead for the next-generation Reconfigurable Dataflow Unit (RDU); drove hardware/software codesign activities. Architected novel compiler support for mixed precision; led the team to land on a short timeline and enabled improved accuracy for customers. Architected new hardware features to accelerate computer vision models. Bootstrapped a new docs-as-code methodology and created a new dataflow assembly language to enable next-chip architecture spec development. Proposed and implemented a migration of the compiler build from CMake to Bazel to enable >10X speedups for developer workflows. Initiated a collaboration with OpenXLA. Up-leveled the compiler organization by organizing regular knowledge shares and supporting individuals' careers at junior and senior levels. Multiple patents pending.

Senior Hardware Engineer

Google · Sunnyvale, CA

Memory system/NoC, host interface, and inter-chip interconnect architecture, microarchitecture, logic design, and cross-functional technical leadership for multiple generations of Google's Tensor Processing Unit (TPU) datacenter AI accelerator chips (TPUv4i, TPUv4, TPUv5e, TPUv5p, and Trillium). Co-founded the Chip Development Kit (CDK) project which enabled large improvements in development velocity, microarchitecture quality, and verification quality using composable and formally verified libraries along with code generation tools. Pioneered a "correct-by-construction" methodology that has been silicon proven. Led a team of ~15 engineers.

Ph.D. Intern

Microsoft Research · Redmond, WA

Worked in the Sensing and Energy Research Group (SERG) in collaboration with Microsoft Cloud Server Infrastructure. Performance evaluation of memory system fault tolerance schemes for the cloud. Measured and modeled the impact of corrected memory errors on application performance.

Ph.D. Intern

Microsoft Research · Redmond, WA

Worked in the Sensing and Energy Research Group (SERG) in collaboration with Microsoft Cloud Server Infrastructure. Developed X-Mem, an Extensible Memory characterization tool, for exploring the impact of system configurations on cloud server performance.

IP Engineering Intern

Altera (now known as Intel FPGA) · San Jose, CA

RTL design and functional verification of soft IP core to identify malformed PCI Express transaction-layer packets.

Instr. Engr. Co-op

NASA Dryden Flight Research Center (now known as NASA Armstrong FRC) · Edwards AFB, CA

Conducted lab and field tests of GPS and wireless sensor system upgrades for research aircraft.

Flight Syst. Engr. Co-op

NASA Dryden Flight Research Center (now known as NASA Armstrong FRC) · Edwards AFB, CA

Designed, integrated, and documented custom hardware panels for PCBs and wiring harnesses using 3D CAD.

I.T. Intern

Lam Research · Fremont, CA

General I.T. duties, including computer repair and retirement as well as hardware and software troubleshooting.